Model for Delay Faults Based upon Paths
نویسنده
چکیده
Delay testing of combinational logic in a clocked environment is analyzed. A model based upon paths is introduced for delay faults. Any path with a total delay exceeding the clock interval is called a "path fault." This is a global delay fault model because it is associated with an entire path. The more familiar slow-to-rise or slow-to-fall gate delay fault, on the other hand, is a local fault model. A procedure is described which identifies paths which are tested for path faults by a set of patterns. It does not involve delay simulation. The paths so identified are tested for path faults independent of the delays of any individual gate of the network.
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